This invention relates to a semiconductor memory device and more particularly to a clock synchronous type dynamic random access memory (DRAM) with data latch.
2. Description of the Related Art
The structure and operation of a general DRAM are described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 4, APRIL 1991 pp. 479-482 N. Kushiyama et al., "A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation", for example.
However, in the conventional DRAM, since it is necessary to invert the output state of a sense amplifier at the time of data writing in a case where data stored in the memory cell and data input from the exterior are different from each other, the writing operation speed is lowered. That is, when an address signal is input from the exterior, the potential of a word line designated by the row address signal is first set to a high level irrespective of the writing operation or readout operation and data of a memory cell corresponding to the word line is read out to the sense amplifier and latched therein. In this case, if the memory system is set in the writing mode, data input from the exterior is written into the sense amplifier by turning ON a column selecting transistor connected between the sense amplifier and the I/O buffer. At this time, if data read out from the memory cell and data input from the exterior are different from each other, it becomes necessary to invert the output state of the sense amplifier and invert the potential relation of paired bit lines, thereby making the writing time long.
The technique of transferring data to the bit lines before the sense amplifier is activated at the time of writing, the operation of setting the paired bit lines to potentials corresponding to the write data when variations in the potential levels of the paired bit lines are still small and amplifying the potential difference by use of the sense amplifier is described in Jpn. Pat. Appln. KOKAI Publication No. 2-226581 and Jpn. Pat. Appln. KOKAI Publication No. 2-29987. According to this technique, time for inverting the output state of the sense amplifier becomes unnecessary and the writing operation speed is enhanced.
It is strongly required to enhance the data writing speed and reading speed in the DRAM, and in order to meet the requirement, a clock synchronous type device in which data is written or read out in synchronism with a clock signal is used. The clock synchronous type semiconductor memory device is described in IEICE TRANS. ELECTRON, VOL. E77-C, NO. 8 AUGUST 1994 pp. 1303-1315 S. Ohshima et al., "High Speed DRAMs with Innovative Architectures, for example. Further, it takes a longer time when different rows are successively accessed than when the same rows are successively accessed, but in order to prevent the user from noticing the delay in the access, a structure with a data latch is used. In order to use the clock synchronous type structure with data latch, it is necessary to effect the data transfer between the sense amplifier and the data latch in synchronism with the clock signal.
With the above clock synchronous type DRAM with data latch, the current driving ability of the sense amplifier must be larger than the current driving ability of the data latch in order to make it possible to effect the data transfer from the sense amplifier to the data latch (at the time of reading). With the above relation of the current driving ability, an output of the sense amplifier cannot be inverted by an output of the data latch if the timing of activation of the sense amplifier does not match with the data transfer timing at the time of data transfer from the data latch to the sense amplifier (at the time of writing), and there occurs a possibility of writing error. However, in this type of conventional DRAM, the sense amplifier activates the internal timer at the time of fall of the RAS signal and this operation is not synchronized with the clock signal. On the other hand, since the data transfer is effected in synchronism with the clock signal, it is difficult to attain the matching between the above timings.